After watching this video you will have the most important info which will help you to simulate your own PCB layout. We will be using Cadence Sigrity, SystemSI, SPEED2000 and Allegro. iMX6 Rex project: http://www.imx6rex.com/ Github with files: https://github.com/FEDEVEL/board-imx6rex-module-in-cadence Would you like to support me in what I do? It's simple: - you will help … Continue reading How To Do DDR3 Memory PCB Layout Simulation – Step by Step Tutorial
This video includes also explanation about setting up rules and how to do length matching of individual branches / segments.
This video explains how to setup xSignals and do length matching in Fly-by & T-Branch DDR3 memory layout. It also shows how to setup xSignals with passive components (e.g. series termination resistors or AC coupling capacitors) + adds some comments on how xSignals calculates the length and what is useful about them. Try the examples … Continue reading Altium – How to use xSignals ( in Fly-By, T-Branch + Other useful things )
Have you been thinking about leaving some of the memory chips un-fitted on your board and you were not sure if it's possible or how the layout should be done to support it? I have received this question for couple of times, so I try to share what we tested and what we do. We … Continue reading DDR3 layout vs Memory chip fitting
You will learn how to do High Speed Design PCB Layout in Altium (DDR3, PCIE, SATA, Ethernet, etc.).
This picture shows DDR3 memory groups and length matching requirements between them.
Choosing the correct VIA for a particular memory group and deciding on how PCB layers will be used can make DDR3 layout a lot easier.
Every hardware design engineer wants to be sure that the DDR3 memory interface is working correctly. Here are some real examples of DDR3 memory testing >>
What is the best way to test DDR3 interface by running a memory test? STEP 1: Do ...
A unique view on PCB layout process. Screenshots captured during iMX6 Module design ... and more will come ...