Review of Server PCB Layout & Schematic – Part 4: PCI Express (PCIE)

This video is about: Zig-Zag routing, Stitching VIAs, Stub in PINs, Holes in GND under PADS and around VIAs, Port 80 & POST Codes Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files - Olympus Intel: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download Cadence document: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/pcb-design-analysis/pcb-west-2016-new-techniques-address-layout-challenges-high-speed-routing-cp.pdf 100Gbps design guidlines document: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an684.pdf

How To Do DDR3 Memory PCB Layout Simulation – Step by Step Tutorial

After watching this video you will have the most important info which will help you to simulate your own PCB layout. We will be using Cadence Sigrity, SystemSI, SPEED2000 and Allegro. iMX6 Rex project: http://www.imx6rex.com/ Github with files: https://github.com/FEDEVEL/board-imx6rex-module-in-cadence Would you like to support me in what I do? It's simple: - you will help … Continue reading How To Do DDR3 Memory PCB Layout Simulation – Step by Step Tutorial