This video explains how I was doing DDR3 layout and length matching in Altium Designer.
Please LIKE, Share, ReTweet. Thank you.
Altium Designer – DDR3 routing and PCB layout video
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This video explains how I was doing DDR3 layout and length matching in Altium Designer.
Please LIKE, Share, ReTweet. Thank you.
Welldone Blog 
Dude this is awesome, thanks for sharing this kind of experience I would totally love to see the 3D preview of this. I am starting with PCB design and have only been facing 2 layer boards. Is there a University where they have a course about complex PCB designs? How did you learn all these stuff? cheers man!!
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Thank you for your comment Yoshiki.
Just work on as many designs as you can. Each design has it’s own challenges and with each design you will learn something new.
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Nice as difficult… I’m about to design something similar with an FPGA, the lenght matching is not easy as AD don’t help too much.
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I agree. Altium is not ideal for high speed design – yet. On other hand, I save a lot of time on component managment, then I am ok with it.
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Nice Design, I am working with Altium for about 7 years now (yes been there from the protel era) I do however would like to have your comments on the SI side of this design. how do you route your planes? and at what speeds do these DDR3 run?
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Hi Paulus, thank you very much. These are 900MHz (DDR3-1800). If possible, I normally use something like SIG / GND / SIG (High Speed stuff) / GND (or possibly one of VCCs – a whole plane) / VCC planes (possibly mixed with slow tracks) / VCC planes / GND (or possibly one of VCCs – a whole plane) / SIG (High Speed stuff) / GND / SIG Hope it helps 😉
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Thanks for the info, I normally use top/plane/plane/ sig/sig/plane/plane/sig etc.
because its hard to keep solid plane references all the time.
It is good to hear that you reach 900Mhz with this I am currently running designs with 533Mhz. so my initial design was with all rounded arcs in the matching. but it seems this is not needed. (makes the matching a lot easier!)
althoug I have a lot of restrictions (no blind/buried/microvia’s) you give me hope 🙂
by the way do you terminate you address lines? it seems there is no way to find clear info on if it is needed or not. and mostly it is simulated to figure out weather or not is needed.
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I always check with chip manufacturer if address termination resistors are required, but I get always same “safe” answer – they recommend to use them. Once the design with termination resistors is manufactured, I do not investigate if it will work without them.
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I am watching this video over and over again to figure how you do this, the thing is when I compare the DDR2/3 excel you made (which is a really great reference) I am curious on via length.. shouldn’t it matter? most boards are 1.6mm so a top bottom via would add 1.6mm and depending on layer stacks internal via’s should be shorter..
I added via lenght to the calculations and it’s a whole different ball game from there… altium does not take those into accountAlso the length matching is with 45 degree angles is that no problem for these high speeds?
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That’s exactly why I route all the signals within one group exactly same way – you know, all the signals in one group goes from L1 to L3 and then L10 …. all of them goes through same number of vias and same length in vias. Advantage is – stackup thickness will not influence it – the relative length of all the signals will stay same. Hmm, I dont understand your question about 45 degree.
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Point well made! it is better to do so if possible, in my case it is not so I need to do it by calculating it. (my goal is to use only through hole via’s (do not ask why lol))
the 45 degree questions was for the mitering. I usually use arcs and rounded corners, but seeing that your design only uses 45 Degree angles and works @ 900Mhz I think I can save a lot of time by leaving the arcs behind.
(I hope you do not mind me asking so many questions)
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45 Deg corners are fine. BTW the groups should be routed the way as I described. I have done it before with through hole vias only – no problem. On other side I have seen a design were the signals within a group are not routed same way and it doesn’t work reliably.
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Hello, Robert!
Thank you for lessons! I would like to repeat your design with DM8168 for DDR3 4Gb x16. Does your design work reliable?
Thank you!
Sergej.
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Yes, works perfectly and reliably.
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Ok. Thank you!
I will put all chips on top layer, because we have enough space, but layer count maybe less than 12.
Thank you!
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Hi Robert.
Thank you for information.
Does your design work reliable in maximum clock rate(DDR3-1800)?
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Yes it does work reliably at maximum clock. Have a great day 🙂
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Dear Robert!
Have you used in your design pin swap on CPU side?
As I understand from video, you use only 8 layers?
What is the size of via do you use?
Thank you!
Sergej.
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Hello Sergej,
have a look at our iMX6Rex module open source project. It is a little bit different board than in the video, but you can download the complete Atlium project and it can answer a lot of your questions: http://www.imx6rex.com/
– Pins swap: I do this manually, just swap the netlables directly in the schematic on the memory side.
– that was a 12 layer pcb
– Here is info about the VIAs which we normally use: http://www.fedevel.com/welldoneblog/2011/05/pcb-stackup-example-minimum-track-clearance-via/
I hope this helps. If you have any other questions, the best is to use our forum here: http://www.fedevel.com/designhelp/
– Robert
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Thank you for fast reply!
I will analyze your refereces…
Oh…, as I see you use in iMX blind/burried vias, after that I saw what on DM8168 PCB you also use blind/burried vias… Ok, I got it. As I undersand, in this designs with mirrored DDR3 IC layout on both sides of PCB, it is impossible to do without blind/burried vias…?
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If you have two memories on top of each other and they are connected to different data signals, you may want to use uVIAs. However, if they are both connected to the same data signals, you can use through hole VIAs.
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i learn lot from your YouTube channel. draw some picture which clearly give ideas about routing and length match.
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