DDR, DDR2 and DDR3 memory reference layouts can be found on JEDEC website. They provide schematics and PCB brd files (requires registration). It’s very useful to see how JEDEC does the layout.
For example see difference in address routing (yellow colour) for DDR2 (T-branch topology) and DDR3 (fly-by topology) :
Picture: DDR2 2 Rank x16 example
Picture: DDR3 2 Rank x16 planar example
You will need Allegro FREE Physical Viewer (free, but requires registration) to open the brd files. In case you have never used Allegro before, you may want to watch Very simple tutorial – How to start with Cadence Allegro.
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11 thoughts on “DDR, DDR2 and DDR3 – PCB layout examples”
Reproduced the article
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Awesome article! BTW: is it possible to layout DDR3-1600 on 2-layer board? which topology is you prefer for 2-layer board, T-topo or Fly-By?
Hi, I don’t think that would work 😉
(if by 2 layer you mean Top, Bottom and that’s it)
I am also surprised, but seems some HiDTV chip already has 2-layer DDR3 1600 solution….
How about designing the DDR3 on the same 10-layer board with the uP, with the placement something like below? 2 Memory on top and 2 memory below the uP, using Fly-by?
It is possible, but there are better ways to place it. Of course, you probably have a reason for this placement.
for ddr board which topology is best ?? topology depends on placement
Hi, generally it depends on memory type. But always read design guides as manufacturers of chips (CPU, FPGA, …) specificaly say what topology should be use as it also depends on memory controller capabilities.