I have used this spreadsheet to calculate DDR2 length for one of projects. I hope it helps to other people.
Please LIKE, Share, ReTweet. Thank you.
I have used this spreadsheet to calculate DDR2 length for one of projects. I hope it helps to other people.
Please LIKE, Share, ReTweet. Thank you.
Thank you Robert for sharing your spreadsheet. I’m developing an ARM based board (ATMEL SAMA5D3 processor) with DDR2 memory and I’m using your spreadsheet. I’m having a look at design guides, dev kit pcb files and also imx6rex board (I know is DDR3).
My question is, what is the minimun trace spacing in order to minimize crosstalk?
ATMEL says:
– In the same data lane: 8 to 12 mil
– Data lane signal to other signals: > 20 mil
– ADDR/CMD/CTL/CK to other signals: > 20 mil
but in imx6rex board, clearance seems to be about 4 mil.
Thank you
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Hello Emanuele. It depends on your stackup. Some design guides recommend relative value – here is an example: 5H (Clock), 4H (data), 3H (address) where H is distance from the ground reference plane. Hope it helps.
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